Mitsubishi Electric Q26UD(E)HCPU - Page 533

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APPENDICES
A
Appendix 3 List of Special Register Areas
SD305
Device
assignment
(Index
register)
16 bit
modification
of Number of
points
assigned for
Z
• Stores the number of points of index register (Z) used for the
16-bit modification area. (Depending on the index
modification setting for ZR in the parameter setting.)
• When "Use ZZ" is selected for "Indexing Setting for Device"
in the Device tab of "PLC parameter", FFFF
H
is stored.
S (Initial) New
QnU
LCPU
SD306 Device
assignment
(Same as
parameter
contents)
Number of
points
assigned for
ZR (for
extension)
The number of points for ZR is stored (except the number of
points of extended data register (D) and extended link register
(W)). The number of points assigned to ZR is stored into this
register only when 1k point or more is set for the extended
data register (D) or extended link register (W).
S (Initial) New
QnU
*7
LCPU
SD307
SD308 Device
assignment
(assignmen
t including
the number
of points
set to the
extended
data
register (D)
and
extended
link register
(W))
Number of
points
assigned for
D (for inside
+ for
extension)
The total points of the data register (D) in the internal device
memory area and the extended data register (D) are stored as
a 32-bit binary value.
S (Initial) New
QnU
*7
LCPU
SD309
SD310
Number of
points
assigned for
W (for inside
+ for
extension)
The total points of the link register (W) in the internal device
memory area and the extended link register (W) are stored as
a 32-bit binary value.
SD311
SD315
Time
reserved
for
communica
tion
processing
Time
reserved for
communicati
on
processing
• This register specifies the amount of processing time for
communication with a programming tool or another module.
• The greater the value specified is, the shorter the response
time for communication with another (such as a
programming tool or serial communication module) is.
However, scan time will increase by the specified time.
• Setting range: 1 to 100ms
A setting outside the above range is regarded as no setting.
UNew
Q00J/Q00/Q01
Qn(H)
QnPH
QnPRH
SD329
Online
change
(inactive
block)
target block
number
SFC block
number
• While online change (inactive block) is executed (SM329 is
on.), this register stores the target SFC block number.
• In other than the above status, this register stores FFFF
H
.
S (Status
change)
New
QnU
*8
LCPU
*13
SD339
Latch clear
operation
setting
Latch clear
operation
setting
When 5A01
H
is set to SD339, SM339 will be valid. After the
latch clear processing ends, this register is cleared to 0.
S (Status
change)/U
New
QnUDV
*12
LCPU
*11
Number Name Meaning Explanation
Set by
(When Set)
Corresponding
ACPU
D9
Corresponding
CPU