September 9, 2011 68009482001
2-4 Theory of Operation: System Communications Overview
The Mainboard also converts transmit audio input signals from the Consolette back panel to SSI
using a CODEC. Moreover, received audio from the transceiver is sent to the Mainboard on this CAN
bus. The FPGA on the Mainboard converts the CAN data back to SSI and routes the signal to a
CODEC. The CODEC converts the audio back to an analog signal and routes the signal to the
various audio interface connectors on the rear panel of the Consolette.
2.3.2 CAN Bus and Auto-Termination
The CAN bus has many benefits for long-distance and robust communication of digital signals.
However, in order to function correctly in a multi-node system, cable termination must exist only at
the end nodes. Any termination in the middle can greatly distort the CAN signals, reducing the
effectiveness of the CAN bus. When a cable is not present in a CAN connector, the termination
circuit defaults to shorting a 120Ohm load across the CAN_HIGH and CAN_LOW signals for each
CAN bus. When all CAN connectors on a device are used, meaning that the device is in the middle
of the CAN bus, the auto-termination circuit removes the termination from that device. The
Consolette contains internal cabling to properly connect the CAN bus to all devices necessary.
NOTE: The CAN cables must always be attached at both ends to a device. The cable detection
architecture presumes all cables attached have a device at both ends. The signal integrity of
the CAN data stream can be degraded if the system is not installed in this manner.
2.3.3 Nautilus FPGA
The Nautilus FPGA (U900) requires three voltages which are 1.5V core voltage, 3.3V and 2.85V I/O
voltages. It also requires a 16 MHz clock, which is used to generate internal frequencies (done by
using internal multipliers and dividers). If either voltage or clock is not present at power on then the
FPGA will not work properly. The core voltage and I/O voltage banks can power on in any sequence
and the core voltage draws up to 500 mA at power on.
The FPGA is programmed by the OMAP using the SPI bus each time the Mainboard powers on.
Upon completion of programming, the signal NAUT_CONFIG_DONE goes high. A failure in
programming the FPGA will display FL 1C-86 error code on the Consolette LCD display.
2.3.4 Microcontroller and Memory
The Consolette Mainboard contains a Texas Instruments OMAP microcontroller, reference
designator U400. Two clocks are supplied to the microcontroller, a 32 kHz clock and 12 MHz clock. A
buffered version of the 32 kHz clock is visible on the testpoint “32k_out” briefly on startup. This pin is
later reconfigured by software as a reset pin used by the OMAP. The microcontroller contains an
integrated synchronous serial interface (SSI), serial peripheral interface (SPI), I2C interface, LCD
controller, keypad controller, UART, and USB controllers. SSI is used for the CAN bus
communication. SPI is used to transfer data to and from devices such as the Nautilus FPGA and the
RX Audio Attenuator IC. I2C is used to transfer data to and from devices such as the CODEC, the
Power Control IC, and the Real-Time Clock IC.
Switches are used to disconnect the OMAP SSI bus from the rest of the system. These switches are
U403, U404, U407, and U408. In addition, filters FL400 and FL401 are used to filter noise from the
SSI clock and frame sync lines. Finally, U410 is a Schmitt trigger used to square up the clock and
frame sync lines before these signals reach OMAP.
A NOR Flash memory device, U301, is used to store Mainboard host code and non-volatile system
variables. A DDR SDRAM memory device, U300, is used for volatile code and variables. Neither of
these memory devices is field-repairable. Both devices are located near the OMAP processor under
shield SH400.
Pull-up and pull-down resistors are used to provide software with a board revision ID. These
resistors are located below the microcontroller shield SH400.
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