Motorola CDM Series - 3.0 UHF Band 2 (450-512;520 MHz) 25-40 W LDMOS Transmitter Power Amplifier (PA) 40 W

UHF Band 2 (450–512/520 MHz) 25–40 W LDMOS Transmitter Power Amplifier (PA) 40 W Section 13: 2-3
6881091C63-F
20/25 kHz channel spacing, or FL3111 and FL3113/F3115 for 12.5 kHz channel spacing. These
pairs are selectable via BWSELECT. The filtered output from the ceramic filters is applied to the
limiter input pin of the IF IC (pin 14).
The IF IC contains a quadrature detector using a ceramic phase-shift element (Y3102) to provide
audio detection. Internal amplification provides an audio output level of 120 mV rms (at 60%
deviation) from U3103, pin 8 (DISCAUDIO) which is fed to ASFIC_CMP U0221, pin 2 (part of the
controller circuits).
A Receive Signal Strength Indicator (RSSI) signal is available at U3101, pin 5, which has a dynamic
range of 70 dB. The RSSI signal is interpreted by the µP (U0101, pin 63) and is available at
accessory connector J0501-15.
3.0 UHF Band 2 (450–512/520 MHz) 25–40 W LDMOS Transmitter
Power Amplifier (PA) 40 W
The radio’s 40W PA is a three-stage amplifier used to amplify the output from the VCOBIC to the
radio transmit level. All three stages utilize LDMOS technology. The gain of the first stage (U5401) is
adjustable, controlled by pin 4 of PCIC (U5501). It is followed by an LDMOS stage (Q5421) and
LDMOS final stage (Q5441).
Figure 13-2 UHF Transmitter Block Diagram
Devices U5401, Q5421 and Q5441 are surface mounted. A pressure pad between the board and
the radio’s cover provides good thermal contact between the devices and the chassis.
PCIC
Pin Diode
Antenna
Switch
RF Jack
Antenna
Harmonic
Filter
Power
Sense
PA-Final
Stage
PA
Driver
From VCO
Controlled
Stage
Vcontrol
Bias 1
Bias 2
To Microprocessor
Temperature
Sense
SPI BUS
ASFIC_CMP
PA
PWR
SET
To Microprocessor
& Bias 3