Section 3: 1-8 Controller Circuits
Section : 6881091C63-F
1.12 Normal Microprocessor Operation
For this radio, the µP is configured to operate in one of two modes, expanded and bootstrap. In
expanded mode the µP uses external memory devices to operate, whereas in bootstrap operation
the µP uses only its internal memory. In normal operation of the radio the µP is operating in
expanded mode as described below.
In expanded mode on this radio, the µP (U0101) has access to 3 external memory devices; U0121
(FLASH EEPROM), U0122 (SRAM), U0111 (EEPROM). Also, within the µP there are 3 kBytes of
internal RAM, as well as logic to select external memory devices.
The external EEPROM (U0111) space contains the information in the radio which is customer
specific, referred to as the codeplug. This information consists of items such as: 1) what band the
radio operates in, 2) what frequencies are assigned to what channel, and 3) tuning information. (See
the particular device subsection for more details.)
The external SRAM (U0122) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off. (See the particular device subsection for more details.)
The FLASH EEPROM contains the actual Radio Operating Software. This software is common to all
open architecture radios within a given model type. For example, trunking radios may have a
different version of software in the FLASH EEPROM than non-trunking radios. (See the particular
device subsection for more details.)
The µP provides an address bus of 16 address lines (ADDR 0 - ADDR 15), and a data bus of 8 data
lines (DATA 0 - DATA 7). There are also 3 control lines; CSPROG (U0101-38) to chip select
U0121-30 (FLASH EEPROM), CSGP2 (U0101-41) to chip select U0122-20 (SRAM) and PG7 R W
(U0101-4) to select whether to read or to write. The external EEPROM (U0111-1), the OPTION
BOARD and EXPANSION BOARD are selected by 3 lines of the µP using address decoder U0141.
The chips ASFIC CMP / FRAC-N / PCIC are selected by line CSX (U0101-2).
When the µP is functioning normally, the address and data lines should be toggling at CMOS logic
levels. Specifically, the logic high levels should be between 4.8 and 5.0 V, and the logic low levels
should be between 0 and 0.2 V. No other intermediate levels should be observed, and the rise and
fall times should be < 30 ns.
The low-order address lines (ADDR 0 – ADDR 7) and the data lines (DATA 0 – DATA 7) should be
toggling at a high rate, e.g., you should set your oscilloscope sweep to 1us/div. or faster to observe
individual pulses. High speed CMOS transitions should also be observed on the µP control lines.
On the µP the lines XIRQ (U0101-48), MODA LIR (U0101-58), MODB VSTPY (U0101-57) and
RESET (U0101-94) should be high at all times during normal operation. Whenever a data or
address line becomes open or shorted to an adjacent line, a common symptom is that the RESET
line goes low periodically, with the period being in the order of 20 ms. In the case of shorted lines
you may also detect the line periodically at an intermediate level, i.e. around 2.5 V when 2 shorted
lines attempt to drive to opposite rails.
The MODA LIR (U0101-58) and MODB VSTPY (U0101-57) inputs to the µP must be at a logic “1”
for it to start executing correctly. After the µP starts execution it will periodically pulse these lines to
determine the desired operating mode. While the Central Processing Unit (CPU) is running, MODA
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction (an
instruction typically requires 2-4 external bus cycles, or memory fetches). However, since it is an
open-drain output, the waveform rise assumes an exponential shape similar to an RC circuit.
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