February 14, 2012 6816985H01-F
4.4-8 700/800 MHz Detailed Theories of Operation: VOCON Functional Blocks
Universal Serial Bus (USB)
The Patriot's USB peripheral, shared by the MCU and the DSP, provides the required buffering and
protocol to communicate on the Universal Serial Bus. The Patriot supports USB slave functionality.
• For receive data: the receive data is routed from the MAKO IC (U701) integrated USB
transceiver. Single ended positive data is generated at U701 pin B9 and is sent to the dual-core
processor pin URXD_RTS. USB data minus comes from U701 pin C9 and is sent to URXD1 of
the dual-core processor.
• For transmit data: the USB data comes out of the Patriot UTXD1 pin and goes to the MAKO IC
pin C8.
General Purpose Input/Output Module (GPIO)
The GPIO (General Purpose Input/Output) Module is shared by the MCU and the DSP. This module
consists of four 16-pin bi-directional ports and a 15 pin bi-directional port. While some of these pins
on these ports are being used for other functions (UART, SPI, SAP, BBP, and Interrupt pins), the
remaining pins on those ports may be programmed to become GPIOs that may be used by either the
DSP or the MCU. Each GPIO pin has up to 8 alternate output functions and up to 4 alternate input
functions. This allows for the GPIO pins to be routed internally to pertinent Patriot modules.
Additionally, the GPIO module adds selectable edge-triggered or level-sensitive interrupt
functionality to the GPIO pins. An example of GPIO pins include the following:
• the LED control signals (RED_LED and GREEN_LED).
4.4.6.1.2 SRAM (U804)
The static RAM (SRAM) is an asynchronous, 1 MB CMOS device that is capable of 70 ns access
speed. It is supplied with 1.8 volts. The SRAM has 19 address lines and 16 data lines connected to
the External Interface Module (EIM) of the Patriot IC through the ADDR(23:0) and DATA(15:0)
busses.
The SRAM has an active low chip-select EN_CE that is connected to the EIM CS2_N pin. When the
SRAM EN_CE pin is not asserted, the SRAM is in standby mode, which reduces current
consumption.
Two other control signals from the EIM that change the mode of the SRAM are the read/write signal
(R/W), and the output enable signal (OE). The R/W of the EIM is connected to the SRAM EN_WE
pin while the OE signal from the EIM is connected to the SRAM EN_OE pin. The SRAM is in read
mode when the EN_WE pin is not asserted and the EN_OE pin is asserted. The SRAM is in write
mode when the EN_WE pin is asserted, regardless of the state of the EN_OE pin.
The other SRAM pins are the lower byte enable pin EN_BLE and the upper byte enable pin
EN_BHE. These pins are used to determine which byte (EN_BLE controls data lines 0-7 and
EN_BHE controls data lines 8-15) is being used when there is a read or a write request from the
Patriot. The EN_BLE pin is controlled by the EIM EB1_N signal while the EN_BHE pin is controlled
by the EB0_N signal.
4.4.6.1.3 Flash Memory (U803)
The Flash memory IC is a 8-megabyte CMOS device with simultaneous read/write or simultaneous
read/erase operation capabilities with 70 ns access speed. It is supplied with 1.8 volts. The Flash
memory has its 22 address lines and 16 data lines connected to the EIM of the Patriot IC through the
ADDR(23:0) and DATA(15:0) busses. The Flash memory contains host firmware, DSP firmware,
codeplug data, and tuning values.
To Next Page
Loading...
