6816985H01-F February 14, 2012
900 MHz Detailed Theories of Operation: Receiver 4.5-3
4.5.4 Receiver
The receiver consists of the following:
•Front end
• Back end
4.5.4.1 Front End
For the purposes of this discussion, the receiver front end is defined as being the circuitry from the
antenna switch to the output of the IF crystal filter. The 900 MHz front end converts the received RF
signal to the 1st IF frequency of 109.65 MHz, while at the same time providing for spurious immunity
and adjacent channel selectivity. A review of the interstage components of the front end follows, with
emphasis on troubleshooting considerations.
The received RF signal is passed through antenna switch input matching components, tank
components and output matching components. Both PIN diodes CR101 and CR102 must be back-
biased to properly route the received signal.
The stage following the antenna switch is a 50-ohm, multi-layer ceramic (MLC) varactor-tuned
preselector (FL1). The preselector (FL1) is positioned after the antenna switch to provide the
receiver preamp with some protection against strong signal, out-of-band signals and first-image
suppression.
After the preselector (FL1), the received signal is applied to a 15dB step attenuator to provide
additional protection against strong signals. The attenuator is controlled by a DSP based algorithm
that continuously monitors signal strength. When the ON threshold is exceeded (approximately -
95dBm), the attenuator is activated via a DAC in the PCIC by the host. The attenuator remains
activated until the signal drops below the OFF threshold (approximately -115dBm including the 15dB
attenuation). Hysterisis and timer functions are included in the algorithm to enhance performance.
The algorithm controlling the attenuator is enabled via the CPS for each personality. When the
algorithm is disabled, the attenuator is essentially a short circuit from input to output. After the
attenuator, the received signal is applied to the receiver preamp, Q1. The preamp is a transistor,
which has been biased and matched for optimum intermodulation (IM), noise figure (NF), and gain
performance. Components L4 and C1 match the input (gate 1) of the amp to the first preselector
output, while D800 provides some breakdown protection for Q1. The output of the amp’s second
MLC preselector is matched to C8, L6, and C5. The preamp is supplied by a 3V analog regulator and
is biased at approximately 0.81Vdc at the base and 1.84Vdc at the collector. The L1 and C3 network
provide improved third order linearity at low.
The output of the amp is matched to a second preselector (FL2) of the type previously discussed.
The subsequent stage in the receiver chain is the 1st mixer U1, which uses low-side injection to
convert the RF carrier to an intermediate frequency (IF) of 109.65 MHz. Since low-side injection is
used in the 900 MHz band, the LO frequency is offset below the RF carrier by 109.65 MHz, or Flo =
Frf - 109.65 MHz. The mixer utilizes Bi-CMOS technology in a double-balanced, Gilbert Cell
configuration.
A balun transformer (T1) is used to couple the RF signal into the mixer. The primary winding of T1 is
matched to the preceding stage by coupling capacitor C7. The secondary winding of T1 provides a
differential output. The center tap pin is grounded via a 39-ohm resistor that sets the mixer bias
current. The differential signal is applied directly to the mixer.
The final stage in the receiver front end is a three-pole crystal filter (FL3). The crystal filter provides
some of the receiver’s adjacent channel selectivity. The input to the crystal filter is matched to the 1st
mixer using components L10, C29, L11, C17, L12, and C18. The output of the crystal filter is
matched to the input with components C19, L13, C20, and L14. The crystal filter provides at least
80dB of second image protection and improves IM distortion in the ABACUS III IC.
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