Chapter 4 Analog Input
X Series User Manual 4-34 ni.com
Figure 4-20. AI Sample Clock and AI Convert Clock Improperly Matched;
Leads to Aperiodic Sampling
Figure 4-21. AI Sample Clock and AI Convert Clock Properly Matched
AI Convert Clock Timebase Signal
The AI Convert Clock Timebase (ai/ConvertClockTimebase) signal is
divided down to provide one of the possible sources for AI Convert Clock.
Use one of the following signals as the source of AI Convert Clock Timebase:
• AI Sample Clock Timebase
• 100 MHz Timebase
AI Convert Clock Timebase is not available as an output on the I/O
connector.
AI Hold Complete Event Signal
The AI Hold Complete Event (ai/HoldCompleteEvent) signal generates
apulse after each A/D conversion begins. You can route AI Hold Complete
Event out to any PFI <0..15>, RTSI <0..7>, or PXIe-DSTARC terminal.
The polarity of AI Hold Complete Event is software-selectable, but is
typically configured so that a low-to-high leading edge can clock external
AI multiplexers indicating when the input signal has been sampled and can
be removed.
AI Sample Clock
AI Convert Clock
Sample #1 Sample #2 Sample #3
1 2 3 0
0
Channel Measured
1 2 3 0
AI Sample Clock
AI Convert Clock
Sample #1 Sample #2 Sample #3
Channel Measured 1 2 3 0
1 2 3 0 1 2 3 0
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