National Instruments PCI E Series Programmer's Manual

Chapter 3 Register Map and Descriptions
PCI E Series RLPM 3-24
© National Instruments Corporation
DAQ-STC Register Group
The registers making up the DAQ-STC Register Group configure and control the DAQ-STC
system timing controller ASIC. These registers are described in the DAQ-STC Technical
Reference Manual.
FIFO Strobe Register Group
The three registers making up the FIFO Strobe Register Group are used to clear the three
FIFOs on the PCI E Series.
Configuration Memory Clear Register
Accessing the Configuration Memory Clear Register clears all information in the channel
configuration memory and resets the write pointer to the first location in the memory.
Window Address: 52 (hex)
Type: Write-only
Word Size: 16-bit
Bit Map: Not applicable; no bits used
ADC FIFO Clear Register
Accessing the ADC FIFO Clear Register clears all information in the ADC data FIFO.
Window Address: 53 (hex)
Type: Write-only
Word Size: 16-bit
Bit Map: Not applicable; no bits used
DAC FIFO Clear Register
Accessing the DAC FIFO Clear Register clears all information in the DAC data FIFO.
Note
This Register is not valid for the PCI-6023E, PCI-6032E and PCI-6033E.
Window Address: 54 (hex)
Type: Write-only
Word Size: 16-bit
Bit Map: Not applicable; no bits used

National Instruments PCI E Series Specifications

General

Brand	National Instruments
Model	PCI E Series
Category	I/O Systems
Language	English