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National Instruments Corporation 3-1 PCI E Series RLPM
3
Register Map and Descriptions
This chapter describes in detail the address and function of each of the PCI E Series board
control and status registers.
If you plan to use an application software package such as NI-DAQ, LabVIEW, or
LabWindows/CVI with your PCI E Series board, you need not read this chapter. However,
you gain added insight into your PCI E Series board by reading this chapter.
Register Map
Table 3-1 shows the register map for the PCI E Series boards and gives the register name, the
register offset address, the type of the register (read-only, write-only, or read-and-write), and
the size of the register in bits. Obtain the actual register address by adding the appropriate
register offset to the memory base address of the PCI E Series board.
Registers are grouped in the table by function. Each register group is introduced in the order
shown in Table 3-1, then described in detail, including a bit-by-bit description.
The DAQ-STC has 180 different registers. The more frequently used registers have been
given lower offset addresses and are shown in Table 3-1 as the DAQ-STC Register Group.
The advantage of having lower offset addresses is that they can be accessed directly or
through the DAQ-STC windowed mode. You can access the remaining registers in the
DAQ-STC only in the windowed mode. In this mode, the address of the register is first written
to the Window Address Register. The data to be written is then written to the Window Data
Register. Using windowed mode has the advantage of reducing the address space of the board
from 180 to 32 bytes. However, this reduced address space is at the cost of two write
operations to write data to or two read operations to read data from a register.
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