Chapter 4 Analog Input
© National Instruments Corporation 4-15 NI USB-621x User Manual
software or hardware can stop it once a finite acquisition completes. When
using an internally generated AI Sample Clock, you also can specify a
configurable delay from AI Start Trigger to the first AI Sample Clock pulse.
By default, this delay is set to two ticks of the AI Sample Clock Timebase
signal. When using an externally generated AI Sample Clock, you must
ensure the clock signal is consistent with respect to the timing requirements
of AI Convert Clock. Failure to do so may result in AI Sample Clock pulses
that are masked off and acquisitions with erratic sampling intervals. Refer
to the AI Convert Clock Signal section for more information about the
timing requirements between AI Convert Clock and AI Sample Clock.
Figure 4-8 shows the relationship of AI Sample Clock to AI Start Trigger.
Figure 4-8. AI Sample Clock and AI Start Trigger
AI Sample Clock Timebase Signal
You can route any of the following signals to be the AI Sample Clock
Timebase (ai/SampleClockTimebase) signal:
• 20 MHz Timebase
• 100 kHz Timebase
•
(USB-6210/6211/6215 Devices) PFI <0..3>
•
(USB-6212/6216 Devices) PFI <0..15>
•
(USB-6218 Devices) PFI <0..3>, PFI <8..11>
AI Sample Clock Timebase is not available as an output on the I/O
connector. AI Sample Clock Timebase is divided down to provide one of
the possible sources for AI Sample Clock. You can configure the polarity
selection for AI Sample Clock Timebase as either rising or falling edge.
AI Sample Clock Timebase
AI Start Trigger
AI Sample Clock
Delay
From
Start
Trigger
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