MPC5746R Hardware Design Guide, Rev. 1
Power Supply
NXP Semiconductors14
3.6.1 Behavior of LVD / HVD
The internal LVD circuits monitor the voltage on the corresponding supply. If the supply falls below
defined values, the LVD asserts either a reset or an interrupt. Figure 6 illustrates how the RESET behaves
with different LVD/HVD levels. The LVDs also support hysteresis for the falling and rising trip points.
Although there is an option to disable the LVDs and HVDs following reset, they are capable of being used
in a ‘monitor’ only mode and also capable of generating a safe/interrupt event. The LVDs/HVDs can also
be configured after device initialization, preventing a reset when a supply crosses the LVD threshold,
providing a higher voltage range. The customer application should monitor and verify that the device
voltage supply levels remain in the functional range.
NOTE
VDD_LV internal supply power on reset monitors (POR085_c and
POR098_c) cannot be disabled. These trip points are used during the
power-up phase and must ensure that an absolute lowest voltage threshold
for operation is never crossed. This is not a guarantee that the device will
function down to this level. It is rather a guarantee that the device will be
reset if this level is crossed.
Figure 6. Illustration of LVD/HVD behavior with RESET status
VDD_LV supply
RESET pin state
POR098_c(rising)
POR098_c(falling)
VDD_HV_IO_MAIN, VDD_HV_PMC
LVD_I O, LVD_PMC (risi ng)
HVD_Core (if enabled, falling)
LVD_Core_Hot (rising=falling)
LVD_Core_Hot (rising)
HVD_Core (if enabled, rising)
LVD_IO, LVD_PMC (falling)
To Next Page
Loading...
