Power Supply
MPC5746R Hardware Design Guide, Rev. 1
NXP Semiconductors 15
3.6.2 Power-on reset
The power management controller (PMC) controls the Power-On reset (POR) for the MCU. When the
critical power supplies are below minimum levels, the MCU is held in the POWER-UP phase of the reset
state machine (see the Reset and Boot chapter of the MPC5746R Reference Manual), until the power
supplies have reached their specified levels. Power sequencing is not necessary. When the required voltage
levels have been reached, the reset generation module (RGM) propagates the device through the next steps
of the boot process.
The PMC has three internal power-on reset circuits:
• 1.25 V input supply – This circuit monitors the VDD_LV pin and asserts a reset when the input
supply is below defined values.
— POR085_c monitors the voltage on the 1.25 V input supply on the VDD_LV pin. POR085_c
asserts a reset when the input supply is below defined values.
— POR098_c monitors the voltage on the 1.25 V input supply on the VDD_LV pin. POR098_c
asserts a reset when the input supply is below defined values. The POR098_c trip point makes
sure that the voltage is high enough for LV logic to initialize and recognize RESET assertion,
ensuring the correct logic state. At this point all the LVD circuits become functional.
• 5.0 V input supply – This circuit monitors the VDD_HV_PMC pin and ensures the PORST trip
point is high enough to make sure all the LVD circuits are functional.
— LVD_HV monitors the voltage on the 3.5 - 5.0 V input supply at the VDD_HV_PMC pin, the
actual PMC module supply. The POR trip point is high enough to make sure all the LVD
circuits are functional i.e. to ensure that the VDD_HV_PMC supply is in range to allow all
PMC internal circuits to operate reliably.
• The LVD_VFLASH monitors the flash input voltage and is used to control the power-up sequence,
ensuring the flash memory can be accessed prior to the reset phase 0 being completed.
POR085_c2 and POR098_c2 are used for redundancy. Minimum and maximum values and trigger
conditions for each LVD and HVD monitor can be found in the MPC5746R Data Sheet. See the Reset
chapter in the MPC5746R Reference Manual for PORST/RESET pin functionality.
3.6.3 Low-Voltage (LVD) and High-Voltage Detection (HVD)
• All LVDs and HVDs are capable of generating reset.
• All LVDs and HVDs configured for reset generation cause functional or destructive reset.
MC_RGM PHASE0 is not exited until all destructive reset conditions are cleared.
• The appropriate bits in the PMC registers are set by LVD and HVD events.
• LVD and HVD control is protected by the System-on-Chip (SoC) wide register protection scheme.
• There are user option bits available to allow degrade of configurable LVDs/HVDs from destructive
reset down to functional reset. This is a write once mechanism managed by System Status and
Configuration Module (SSCM) during device initialization.
• When the LVD or the HVD is enabled for destructive reset generation, and a trigger event is
detected, the external PORST pin is driven low.
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