NXP Semiconductors MPC5746R - Page 50

MPC5746R Hardware Design Guide, Rev. 1
Example Communication Peripheral connections
NXP Semiconductors50
NOTE
In MPC5746R, Serial Management Interface FEC_MDIO/FEC_MDC pins
are internally tied up to VDD_HV_IO_MAIN supply domain, which is
usually 5 V. Therefore the user must use a bidirectional level shifter on the
MDIO/MDC pins. Refer the MPC5746R Errata for more information.
As shown in Figure 33, the FEC can interface to a PHY using the 10/100 Mbit/s MII-Lite, RMII or the 10
Mbit/s only 7-wire interface. The FEC signals from the MCU take their voltage level from the
VDD_HV_IO_FEC supply domain. Most PHYs require signals in the 3.3 V range, so the
VDD_HV_IO_FEC should be set accordingly. The FEC signals are summarized in Table 27 and their use
in each interface type is highlighted. Note that the signals required by different PHYs will vary in some
cases for each interface option; see the Data Sheet for your selected PHY.
Table 27. FEC Signal Overview
Signal Name Description Direction MII RMII 7-Wire Port
FEC_COL
1
1
This signal is not available in the MII-Lite interface
Collision Detection I Required Option Required PC[5]
FEC_REF_CLK RMII Reference Clock Output O N/A Required N/A PC[0]
FEC_MDC Management Data Clock O Required N/A N/A PD[8]
FEC_MDIO Management Data Output I/O Required N/A N/A PD[13]
FEC_RXCLK Receive Clock I Required N/A Required PC[12]
FEC_RXDV
2
2
FEC_RXDV in RMII mode generates RXDV and CRS.
Receive Data Valid I Required Required N/A
PC[13]
Carrier Sense
1
I Required Required N/A
FEC_RXD0 Receive Data 0 I Required Required Required PC[7]
FEC_RXD1 Receive Data 1 I Required Required N/A PC[8]
FEC_RXD2 Receive Data 2 I Required N/A N/A PC[9]
FEC_RXD3 Receive Data 3 I Required N/A N/A PC[10]
FEC_RXER
1
Receive Error I Option Option N/A PC[11]
FEC_TXCLK Transmit Clock I Required N/A Required PC[1]
FEC_TXD0 Transmit Data 0 O Required Required Required PC[6]
FEC_TXD1 Transmit Data 1 O Required Required N/A PC[5]
FEC_TXD2 Transmit Data 2 O Required N/A N/A PC[4]
FEC_TXD3 Transmit Data 3 O Required N/A N/A PC[3]
FEC_TXEN Transmit Enable O Required Required Required PC[2]