52
CJ1 and CJ1-H CPU Unit Comparison Section 1-6
Tasks Cyclic execution of
interrupt tasks via
TKON instruction
(called “extra cyclic
tasks”)
Supported.
(Up to 256 extra cyclic
tasks, increasing the total
number of cyclic tasks to
288 max.)
Supported.
(Up to 256 extra cyclic
tasks, increasing the total
number of cyclic tasks to
288 max.)
Not supported.
(No extra cyclic tasks; 32
cyclic tasks max.)
Independent/shared
specifications for
index and data regis-
ters
Supported.
The time to switch between
tasks can be reduced if
shared registers are used.
Supported.
The time to switch between
tasks can be reduced if
shared registers are used.
Not supported.
(Only independent registers
for each task.)
Initialization when
tasks are started
Supported.
Task Startup Flags sup-
ported.
Supported.
Task Startup Flags sup-
ported.
Only Task Flag for first exe-
cution.
Starting subroutines
from multiple tasks
Global subroutines can be
defined that can be called
from more than one task.
Global subroutines can be
defined that can be called
from more than one task.
Not supported.
Scheduled interrupt
interval for scheduled
interrupt tasks
1 ms to 9,999 ms, or 10 ms
to 99,990 ms, in units of 1
ms or 10 ms.
In addition to the previ-
ously supported intervals
(1 ms to 9,999 ms, or 10
ms to 99,990 ms, in units
of 1 ms or 10 ms), an inter-
val of 0.5 ms to 999.9 ms in
units of 0.1 ms is also sup-
ported.
1 ms to 9,999 ms, or 10 ms
to 99,990 ms, in units of 1
ms or 10 ms.
Interrupt
task exe-
cution
timing
during
instruc-
tion exe-
cution
For instruc-
tions other
than the
following
ones
Any instruction that is being executed is interrupted when interrupt task conditions are
met to start the interrupt task. If the cyclic task (including extra cyclic tasks) access
the same data area words as the instruction that was interrupted, data may not be
concurrent. To ensure data concurrency, the DI and EI instructions must be used to
disable and enable interrupts during a specific part of the program.
For BIT
COUNTER
(BCNT) or
BLOCK
TRANS-
FER
(XFER)
instruc-
tions
Interrupt tasks are started only after execution of the
instruction has been completed, ensuring data concur-
rency even when the same data area words are
accessed from the instruction and the interrupt task.
Debug-
ging
Backup to Memory
Cards (simple backup
function)
In addition to the data
listed at the right, data from
Units mounted to the CPU
Rack or Expansion Racks
can also be backed up to
the Memory Card (via
pushbutton on front panel).
This is very effective when
replacing Units. Backup
data includes scan lists for
DeviceNet Units, protocol
macros for Serial Commu-
nications Units, etc.
In addition to the data
listed at the right, data from
Units mounted to the CPU
Rack or Expansion Racks
can also be backed up to
the Memory Card (via
pushbutton on front panel).
This is very effective when
replacing Units. Backup
data includes scan lists for
DeviceNet Units, protocol
macros for Serial Commu-
nications Units, etc.
Only the user program
parameters, and I/O mem-
ory in the CPU Unit.
Automatic user pro-
gram and parameter
area backup to flash
memory
Supported (enabling bat-
tery-free operation without
a Memory Card)
The user program and
parameter area data are
automatically backed up
the flash memory when-
ever they are transferred to
the CPU Unit from the CX-
Programmer, file memory,
etc.
Supported (enabling bat-
tery-free operation without
a Memory Card)
The user program and
parameter area data are
automatically backed up
the flash memory when-
ever they are transferred to
the CPU Unit from the CX-
Programmer, file memory,
etc.
Not supported.
Item CJ1-H CPU Unit
(CJ1H-CPU6@H)
CJ1M CPU Unit
(CJ1M-CPU@2/CPU@3)
CJ1 CPU Unit
(CJ1G-CPU4@)
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