Omron CJ1G/H-CPU series - Page 88

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CJ1 and CJ1-H CPU Unit Comparison Section 1-6
Opera-
tion when
Unit
doesn’t
complete
startup
process
CPU Unit startup Starting or not starting
(standby) the CPU Unit in
MONITOR or RUN mode
even if a Unit has not com-
pleted startup processing
can be specified in the
PLC Setup.
Starting or not starting
(standby) the CPU Unit in
MONITOR or RUN mode
even if a Unit has not com-
pleted startup processing
can be specified in the
PLC Setup.
CPU Unit standby (fixed)
Disabling power interruptions in
program sections
Supported.
Instructions between DI
and EI are executed with-
out performing power OFF
processing even if a power
interruption has been
detected and confirmed.
Supported.
Instructions between DI
and EI are executed with-
out performing power OFF
processing even if a power
interruption has been
detected and confirmed.
Not supported.
Condition Flag operation The statuses of the Equals,
Negative, and Error Flags
are maintained for execu-
tion of the following instruc-
tions.
TIM, TIMH, TMHH, CNT,
IL, ILC, JMP0, JME0,
XCHG, XCGL, MOVR,
input comparison instruc-
tions, CMP, CMPL, CPS,
CPSL, TST, TSTN, STC,
and CLC.
The statuses of the Equals,
Negative, and Error Flags
are maintained for execu-
tion of the following instruc-
tions.
TIM, TIMH, TMHH, CNT,
IL, ILC, JMP0, JME0,
XCHG, XCGL, MOVR,
input comparison instruc-
tions, CMP, CMPL, CPS,
CPSL, TST, TSTN, STC,
and CLC.
The Equals, Negative, and
Error Flags are turned OFF
after executing the following
instructions.
TIM, TIMH, TMHH, CNT, IL,
ILC, JMP0, JME0, XCHG,
XCGL, MOVR, input com-
parison instructions, CMP,
CMPL, CPS, CPSL, TST,
TSTN, STC, and CLC.
Built-in I/O Not supported. CJ1M-CPU2@ Not supported.
Serial PLC Link Not supported. Supported. Not supported.
0.1-ms scheduled interrupts Not supported. Supported. Not supported.
Battery CPM2A-BAT01 CJ1W-BAT01 CPM2A-BAT01
Item CJ1-H CPU Unit
(CJ1H-CPU6@H)
CJ1M CPU Unit
(CJ1M-CPU@2/CPU@3)
CJ1 CPU Unit
(CJ1G-CPU4@)