Appendix BSpecifications
66
CPU Specifications
Main Control Element MPU, CMOS, LS-TTL
Programming Method Ladder diagram
Instruction Length 1 address/instruction, 1 to 4 words/instruction
Number of Instructions 145 (12 basic instructions + 133 special instructions)
C200H-CPU11 159 (12 basic instructions + 147 special instructions)
Execution Time Basic instructions: 0.75 to 2.25 ms Special instructions: 34 to 724 ms
Memory Capacity 6,974 words (with 8k-word memory)
I/O bits 480
(00000 through 02915)
I/O Units mounted
to Remote I/O Slave
Special I/O Units
1,600
Optical I/O Units
and I/O Terminals
512
IR bits
3,296
(03000 through 23515)
Racks 800 (05000
through 09915)
(10000 through
19915)
(20000 through
23115)
SR bits
312 (23600 through 25507)
TR bits 8 (TR 0 through 7)
HR bits 1,600 (HR 0000 through 9915)
AR bits 448 (AR 0000 through 2715
LR bits 1,024 (LR 0000 through 6315)
Timers/Counters 512 (TIM/CNT 000 through 511) TIMs: 0 through 999.9 s
TIMHs: 0 through 99.99 s CNT: 0 through 9999 counts
DM words Read/write: 1,000 (DM 0000 through 0999)
Read only: 1,000 (DM 1000 through 1999) DM area is in Memory Pack.
RUN Output Contacts are closed while PC is in RUN mode and operating.
Max. switching capacity: 2A 250 VAC (resistive load)
0.5 A 250 VAC (inductive load, cos of phase angle = 0.4)
2 A 24 VDC
Memory Protection Status of HR bits, AR bits, preset value of counters (CNT), and contents of data memory
(DM) are retained during power failure. Length of memory protection depends on the
Memory Pack model being used (refer to
Section 2-6 Memory Packs
).
Self-diagnostic Functions CPU failure (watchdog timer) Battery failure
Cycle time error Memory failure
I/O bus failure Host Link error
Remote I/O error, etc.
Program Check Program check (executed on start of RUN operation):
END missing Instruction errors
(Program can be checked by Programming Console or GPC at three levels.)
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