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Philips 32PFL5605D/78 - Circuit Descriptions

Philips 32PFL5605D/78
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Circuit Descriptions
EN 29LC9.3L LA 7.
2010-Mar-26
7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
7.2 Power Architecture
Notes:
•Only new circuits (circuits that are not published recently)
are described.
Figures can deviate slightly from the actual situation, due
to different set executions.
For a good understanding of the following circuit
descriptions, please use chapter 9. Block Diagrams
and
10. Circuit Diagrams and PWB Layouts
. Where necessary,
you will find a separate drawing for clarification.
7.1 Introduction
The LC9.3L LA chassis is based on the LC9.2L LA chassis with
added TCON and Ambilight circuitry integrated on the SSB. For
all other circuitry, refer to the LC9.1/LC9.2L LA Service Manual.
7.1.1 Architecture Overview
For details about the chassis block diagrams refer to chapter
Block Diagrams
. An overview of the architecture can be found
in Figure 7-1
and Figure 7-2.
Figure 7-1 Architecture LC9.3L LA chassis - general
18970_201_100325.eps
100325
GDDR3
128MB
Tuner
SHARP NIM
MediaTek
MT5392
Digital Colour Decoder
10-bit video
4-field HD MADI
(MPEG2/MPEG4)
HD-DNM
FRC 100/120Hz
FLASH
128MB
TDA8932
CLASS D
2Ch Audio Amp
SPDIF
RF in (Antenna)
RF in (Cable)
CVBS
SIF
TS in
ADV3002
MUX
HDMI 1
HDMI 2
HDMI 3
(Reserved)
HDMI Side
GDDR3
128MB
32
Reserved
LPC2103
Sharp DFR
Timing Control
DFR Panel
LED / CCFL
2K10
Ambilight
Module
USB2.0