PL3 Series Service Manual 33
TD-000274-00 Rev. A
Figure 3.3 Dead time between one pulse turning off and the other
turning on should be about 20–30 ns at the 5 V level.
Figure 3.4 The clock drive logic signals.Figure 3.2 FET gate drive waveforms
the wave shapes are normal and match each other well. Each gate’s
pulse train should be a rounded square wave reaching ±15 V. Note
how the waveform flattens slightly as the voltage passes through
zero (this controls the dead time between the IGBTs’ alternating
turn-off and turn-on).
If the pulse train waveforms are not correct or not present, see
“Troubleshooting switch-mode supply control circuit problems.”
Failed output FETs: If you suspect that the output switching FETs
Q10 and Q11 (channel 1; QSC part # QD-000318-00) or Q58 and Q59
(channel 2; same part number) may be blown or shorted:
• Check each FET in circuit by measuring the resistance between
its gate and its source. Shorted devices will measure less than 1
ohm.
• When replacing FETs, also check their associated gate drive
resistors, IC driver, diode, etc. For example, if Q10 is shorted,
check D10, R60, R61, and U17.
With the AC voltage completely shut off, check the gate drive signal
at each FET by using the service fixture to power the control circuits
via TEST PORT-A and TEST PORT-B. Confirm that the signals on the
FET gates are normal square waves at 250 kHz, alternating between
0 and +12 V (see Figure 3.2), before replacing the heat sink.
CAUTION: Voltage—even residual amounts—on the main supply
rails can cause high current surges into a grounded scope probe
when it is connected to the FET sources. To avoid this, use only
isolated scope probes to look at gate drive signals when the main
power supply is operating.
With FETs in place (powered by the service fixture), each gate drive
should display a similar square-wave shape, with pulses alternating
between zero and +12 V, with a slightly rounded leading edge and
steeper falling edge as shown in Figure 3.2.
If there is any signal into the modulator, you should also observe
some pulse-width modulation (PWM).
You should observe a slight “dead time” between one gate’s shutoff
and the other’s turn-on (see Figure 3.3). The pulse shutting off
should pass thru 5 V about 20–30 ns before the pulse turning on
does (the two traces should cross each other near zero volts). This
helps ensure that both FETs on a channel output never turn on
simultaneously.
Check the gate drive resistors and the turn-off diode if the slopes or
dead time are wrong.
If the waveforms are not correct or not even present, see “Trouble-
shooting Power FET Control Circuit Problems.”
3.1 PL380: Symptoms, causes, and remedies (continued)
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