PL3 Series Service Manual 35
TD-000274-00 Rev. A
Figure 3.6 Triangle wave at comparator inputs (pin 2 of U8 and U28).
Figure 3.7 Triangle wave with supply rails energized.
0–12 V square waves, with a slightly rounded leading edge and
steeper falling edge (see Figure 3.2).
If there is any signal into the modulator, you should also observe
some pulse-width modulation (PWM).
You should observe a slight “dead time” between one gate’s shutoff
and the other’s turn-on (see Figure 3.3). The pulse shutting off
should pass through 5 V about 20–30 ns before the pulse turning on
does (the two traces should cross each other near zero volts). This
helps ensure that both FETs on a channel output never turn on
simultaneously.
Gate drive issues: Each FET is switched on and off by a specific
isolated gate drive signal that uses the source terminal as a
reference. The FET sources are at different potentials, and each
gate drive circuit requires its own 25 V power supply. Therefore,
each gate drive and supply has a voltage shifting scheme appropri-
ate for its location in the circuit. For example, the gate drive for the
low-side (negative) FET, Q11 (schematic: see sheet
“Amp Ch A,
PL380,”
zone C-3), uses the -185 V rail (at the FET source), not
ground, as a reference. Therefore, the gate drive power derives from
capacitively coupling power pulses from the ground-referenced
housekeeping transformer tap via C262 and C263 (schematic: see
sheet
“Supply, PL380,”
zone C-3). The pulses are rectified by D94
and D95 and place about 25 V on C261 and C284. For channel 2, the
voltage at LO-SIDE GATE-B derives from an identical circuit
(schematic: zone C-2).
The source on each high-side (positive) FETs, Q10 on channel 1 and
Q58 on channel 2, must alternate between the positive and negative
rail voltages. The gate drive circuitry, therefore, is powered via a
coupling transformer, T3 (schematic: see sheet
“Supply, PL380,”
zone A-4), a low-capacitance 1:1:1 gate drive transformer whose
primary is coupled to the 16 V housekeeping supply tap, with each
secondary connected to rectifiers shown (schematic: zone A-3) that
provide 25 V of floating power to each high-side gate drive.
One FET gate drive does not work
The Channel 1 gate drive circuitry is shown on schematic sheet
“Amp Ch A, PL380,”
zones D-4 and C-4. Channel 2’s is on
“Amp Ch
B, PL380,”
zones D-3, D-4, C-3, and C-4.
If one FET gate drive is working but not the other, you only have to
troubleshoot the defective one. You can use the one that works as a
reference, though.
• With your voltmeter, check and confirm the gate drive supply
voltages, measured with respect to the reference
(pin 2 of the
MC7812CT; pins 2, 3, 6, and 7 of the LM78L05)
of each regulator.
There should be approximately +25 V (unregulated) at the inputs
(pin 1)
of U19 and U20 (channel 1) or U38 and U39 (channel 2),
and +12 V on the outputs
(pin 3)
.
The outputs
(pin 1)
of regulators U14 and U15 (channel 1) or U33
and U34 (channel 2) should be +5 V.
• With your oscilloscope, check and confirm the optocoupler input
signals, with respect to ground.
On channel 1, optocouplers U12 and U13 should receive a 5 V
PWM logic signal at their inputs
(pin 2)
. On channel 2, the
corresponding devices are U31 and U32.
Confirm that U12 and U13 are delivering a 5 V PWM output to
inputs of U17 and U18 (etc). Confirm that U17 and U18 are
delivering 12 V gate drive.
• Undervoltage lockout—Voltage dividers formed by R342 and
R343 (on U17) and R340 and R341 (on U18) hold the respective
“enables”
(pin 3)
low until the 12 V supply has neared full
voltage. Confirm that the values are correct.
3.1 PL380: Symptoms, causes, and remedies (continued)
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