Quectel RM502Q-GL - Page 23

5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 22 / 83
1.8/3.0 V
47
PCIE_RX_M
AI
PCIe receive (-)
48
USIM2_VDD
PO
Power supply for
(U)SIM2 card
USIM1_VDD
1.8/3.0 V
49
PCIE_RX_P
AI
PCIe receive (+)
50
PCIE_RST_N
DI, OD
PCIe reset.
Active LOW.
51
GND
Ground
52
PCIE_CLKREQ_N
DO, OD
PCIe clock request.
Active LOW.
53
PCIE_REFCLK_M
AIO
PCIe reference clock
(-)
54
PCIE_WAKE_N
DO, OD
PCIe wake up
Active LOW.
55
PCIE_REFCLK_P
AIO
PCIe reference clock
(+)
56
RFFE_CLK
2)
DO, PD
Used for external
MIPI IC control
1.8 V
57
GND
Ground
58
RFFE_DATA
2)
DO, PD
Used for external
MIPI IC control
1.8 V
59
LAA_TX_EN*
DO
Notification from SDR
to WLAN while LTE
transmitting
1.8 V
60
WLAN_TX_EN*
DI
Notification from
WLAN to SDR while
transmitting
1.8 V
61
ANTCTL1
DO, PD
Antenna GPIO control
1.8 V
62
COEX_RXD*
DI, PD
LTE/WLAN
coexistence receive
1.8 V
63
ANTCTL2
DO, PD
Antenna GPIO control
1.8 V
64
COEX_TXD*
DO, PD
LTE/WLAN
coexistence transmit
1.8 V
65
RFFE_VIO_1V8
PO
Power supply for
RFFE
1.8 V
Maximum output
current: 50 mA
66
USIM1_DET
1)
DI, PU
(U)SIM1 card
hot-plug detect
1.8 V