Quectel RM502Q-GL - Reset

5G Module Series
RM502Q-GL Hardware Design
RM502Q-GL_Hardware_Design 33 / 83
3.6. Reset
RESET# is an asynchronous and active LOW signal (1.8 V logic level). Whenever this pin is active, the
module will immediately enter Power On Reset (POR) condition.
Please note that triggering the RESET# signal will lead to loss of all data in the modem and removal of
system drivers. It will also disconnect the modem from the network.
Table 12: Definition of RESET# Pin
The module can be reset by pulling down the RESET# pin for 200–980 ms. An open collector/drain driver
or a button can be used to control the RESET# pin.
Host Module
RESET#
PMIC
GPIO
67
VDD 1.8V
Reset pulse
200-980 ms
R1
100k
R3
100k
R2
1k
Q1
NPN
Figure 12: Reference Circuit of RESET# with NPN Driving Circuit
Pin No.
Pin Name
I/O
Description
DC Characteristic
Comment
67
RESET#
DI, PU
Reset the module
Active LOW
V
IH
max = 2.1 V
V
IH
min = 1.3 V
V
IL
max = 0.5 V
Internally pulled up
to 1.8 V with a
100 kΩ resistor