Realtek RTL8169 - Register Descriptions

RTL8169
2002/03/27 Rev.1.21
13
6. Register Descriptions
The RTL8169 provides the following set of operational registers mapped into PCI memory space or I/O space.
Offset
R/W Tag Description
0000h R/W IDR0
ID Register 0: The ID registers 0-5 are only permitted to write by
4-byte access. Read access can be byte, word, or double word access.
The initial value is autoloaded from EEPROM EthernetID field.
0001h R/W IDR1
ID Register 1
0002h R/W IDR2
ID Register 2
0003h R/W IDR3
ID Register 3
0004h R/W IDR4
ID Register 4
0005h R/W IDR5
ID Register 5
0006h-0007h - -
Reserved
0008h R/W MAR0
Multicast Register 0: The MAR registers 0-7 are only permitted to
write by 4-bye access. Read access can be byte, word, or double word
access. Driver is responsible for initializing these registers.
0009h R/W MAR1
Multicast Register 1
000Ah R/W MAR2
Multicast Register 2
000Bh R/W MAR3
Multicast Register 3
000Ch R/W MAR4
Multicast Register 4
000Dh R/W MAR5
Multicast Register 5
000Eh R/W MAR6
Multicast Register 6
000Fh R/W MAR7
Multicast Register 7
0010h-0017h R/W DTCCR
Dump Tally Counter Command Register (64-byte alignment)
0018h-001Fh - -
Reserved
0020h-0027h R/W TNPDS
Transmit Normal Priority Descriptors: Start address (64-bit).
(256-byte alignment)
0028h-002Fh R/W THPDS
Transmit High Priority Descriptors: Start address (64-bit).
(256-byte alignment)
0030h-0033h R/W FLASH
Flash memory read/write register
0034h-0035h R ERBCR
Early Receive (Rx) Byte Count Register
0036h R ERSR
Early Rx Status Register
0037h R/W CR
Command Register
0038h W TPPoll
Transmit Priority Polling register
0039h-003Bh - -
Reserved
003Ch-003Dh R/W IMR
Interrupt Mask Register
003Eh-003Fh R/W ISR
Interrupt Status Register
0040h-0043h R/W TCR
Transmit (Tx) Configuration Register
0044h-0047h R/W RCR
Receive (Rx) Configuration Register
0048h-004Bh R/W TCTR
Timer CounT Register: This register contains a 32-bit
general-purpose timer. Writing any value to this 32-bit register will
reset the original timer and begin the count from zero.
004Ch-004Fh R/W MPC
Missed Packet Counter: This 24-bit counter indicates the number of
packets discarded due to Rx FIFO overflow. After a s/w reset, MPC is
cleared. Only the lower 3 bytes are valid.
When any value is written to MPC, it will be reset.
0050h R/W 9346CR
93C46 (93C56) Command Register
0051h R/W CONFIG0
Configuration Register 0
0052h R/W CONFIG1
Configuration Register 1
0053h R/W CONFIG2
Configuration Register 2
0054h R/W CONFIG3
Configuration Register 3
cont...