RTL8169
2002/03/27 Rev.1.21
27
6.16 CONFIG 5
(Offset 0056h, R/W)
This register, unlike other Config registers, is not protected by 93C46 Command register. I.e. there is no need to enable the
Config register write prior to writing to Config5.
Bit R/W Symbol Description
7 - -
Reserved
6 R/W BWF
Broadcast Wakeup Frame:
1: Enable Broadcast Wakeup Frame with mask bytes of only DID
field = FF FF FF FF FF FF.
0: Default value. Disable Broadcast Wakeup Frame with mask bytes
of only DID field = FF FF FF FF FF FF.
The power-on default value of this bit is 0.
5 R/W MWF
Multicast Wakeup Frame:
1: Enable Multicast Wakeup Frame with mask bytes of only DID
field, which is a multicast address.
0: Default value. Disable Multicast Wakeup Frame with mask bytes
of only DID field, which is a multicast address.
The power-on default value of this bit is 0.
4 R/W UWF
Unicast Wakeup Frame:
1: Enable Unicast Wakeup Frame with mask bytes of only DID
field, which is its own physical address.
0: Default value. Disable Unicast Wakeup Frame with mask bytes
of only DID field, which is its own physical address.
The power-on default value of this bit is 0.
3:2 - -
Reserved
1 R/W LANWake
LANWake Signal Enable/Disable:
1: Enable LANWake signal.
0: Disable LANWake signal.
0 R/W PME_STS
PME_Status bit: Always sticky/can be reset by PCI RST# and
software.
1: The PME_Status bit can be reset by PCI reset or by software.
0: The PME_Status bit can only be reset by software.
Bit1 and bit0 are auto-loaded from the EEPROM Config5 byte to the RTL8169 Config5 register.
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