Realtek RTL8169 - Page 71

RTL8169
2002/03/27 Rev.1.21
71
PCI Clock Specification
0.6Vcc
0.2Vcc
0.4Vcc, peak-to-peak
(minimum)
0.3Vcc
T_high T_low
T_cyc
0.5Vcc
0.4Vcc
3.3V Clock Waveform
CLK (@ Device #1)
CLK (@ Device #2)
T_skew
T_skew
T_skew
V_ih
V_ih
V_il
V_il
V_test
V_test
Clock Skew Diagram
66MHz 33MHz
Symbol Parameter Min Max Min Max Units
Tcyc
CLK Cycle Time
15 30 30
∞
ns
Thigh
CLK High Time
6 11 ns
Tlow
CLK Low Time
6 11 ns
--
CLK Slew Rate
1.5 4 1 4 V/ns
--
RST# Slew Rate
50 - 50 - mV/ns
Tskew
CLK Skew
1 2 ns
Clock and Reset Specifications