Reichert AT550 Service Manual

13900-103 Rev. A Page 21
Figure TT-6, Main Control Block Diagram
Testing (Continued)
R? 10K
VCC enable
asic_reset
r/w
dsp_irq
Host control/addr
XSCK
DATA_VALID
"K" OR "R" VIDEO IN
I/O ENABLE
MOTOR_STATUS I2C_ INT_OUT
Beeper Reset
rd
r/w
dsp_reset
wr
BRQ HBG
REDY
dsp_select
uw
CS0/OE
L Data Valid R Data Valid "R" PP_Data Valid MOTOR_STATUS I2 C_INT
EPROM_CE
RTC_EN BBU_RAM_EN
PP_CE1
I/O ENABLE PP_CE0
RESET
/INTR_TRI_EN
HD VD Video
VCC_BAR
DSP-SHARK ADSP-21062
68MC306
addr/data
Real Time
Clock
SRAM (BBU)
DRAM
EPROM
(Operating
System)
EC-ASIC
(Elliptical Comp.)
DSP RAM
rd
wr
D0-47
A0-15
Video RAM addr/data
Host Port
D0-23 HD0-774FCT
543 (Data) 74FCT 543
(Status)
D0-7DSP/
Control/ HREQ
>
ASIC
Decode
>
To Video Board
Camera drive signals
VIDEO A/D
PIXEL CLOCK
PD0-7
&
FPGA
PEAK PIXEL VALUE
PEAK PIXEL
NUM.OF PIXELS
NUM.OF
LATCH
LATCH
VALUE
OE OE
PIXELS
D0-7 D0-15
40 MHZ
I/O PORT BUFFERSD0-7
A1-8
R/W CONTROL
OE
I/O BOARD CONNECTOR
X,Y,Z MOTOR STOPS(FLAGS)
I2 C BUS
LDATAVALID/RDATAVALID
I2 C BUS
Two Serial Ports
clkin
D0-15
A17-22
OE
(X2)
D16-32 '245
dir
(20H)
(X2) '245
OE
Fixed Addr
<
>
PA0
PA1
>
PA3
POS_CAMERA_SEL
D0-15 A1-23
PCMCIA INTERFACE
>
<
>
IRQ's
16MHZ
32.768KHZ
3.6864MHZ
>
DECODES
A5-7,18-20
<
<
<
>
>
<
>
>
>
<
<
RESET CIRCUIT
RESET
D0-15
D0-7
D0-7
32Kx8
256Kx16
256Kx16
/EN
<
5
Mire_drive Fix_drive
< <
J4
J1
J2
J3
Video Test Header

Reichert AT550 Specifications

General

Brand	Reichert
Model	AT550
Category	Measuring Instruments
Language	English