RL78/G13 CHAPTER 4 PORT FUNCTIONS
R01UH0146EJ0100 Rev.1.00 264
Sep 22, 2011
(5) Port output mode registers (POM0, POM1, POM4, POM5, POM7 to POM9, POM14)
These registers set the output mode of P00, P02 to P04, P10 to P15, P17, P43 to P45, P50, P52 to P55, P71, P74,
P80 to P82, P96, P142 to P144 in 1-bit units.
N-ch open drain output (V
DD tolerance) mode can be selected during serial communication with an external device of
the different potential, and for the SDA00, SDA01, SDA10, SDA11, SDA20, SDA21, SDA30, and SDA31 pins during
simplified I
2
C communication with an external device of the same potential.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-69. Format of Port Input Mode Register (128-pin products)
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM0 0 0 0 POM04 POM03 POM02 0 POM00 F0050H 00H R/W
POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 F0051H 00H R/W
POM4 0 0 POM45 POM44 POM43 0 0 0 F0054H 00H R/W
POM5 0 0 POM55 POM54 POM53 POM52 0 POM50 F0055H 00H R/W
POM7 0 0 0 POM74 0 0 POM71 0 F0057H 00H R/W
POM8 0 0 0 0 0 POM82 POM81 POM80 F0058H 00H R/W
POM9 0 POM96 0 0 0 0 0 0 F0059H 00H R/W
POM14 0 0 0 POM144 POM143 POM142 0 0 F005EH 00H R/W
POMmn
Pmn pin output mode selection
(m = 0, 1, 4, 5, 7 to 9, 14; n = 0 to 7)
0 Normal output mode
1 N-ch open-drain output (VDD tolerance) mode
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