RL78/G13 CHAPTER 6 TIMER ARRAY UNIT
R01UH0146EJ0100 Rev.1.00 354
Sep 22, 2011
(14) Noise filter enable registers 1, 2 (NFEN1, NFEN2)
The NFEN1, NFEN2 registers is used to set whether the noise filter can be used for the timer input signal to each
channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (f
MCK). When the noise filter is OFF, only synchronization is performed with the
CPU/peripheral hardware clock (f
MCK)
Note
.
The NFEN1, NFEN2 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note For details, see 6.5.1 (2) When valid edge of input signal input from the TImn pin is selected (CCSmn
= 1) and 6.5.2 Start timing of counter.
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