RL78/G13 CHAPTER 19 RESET FUNCTION
R01UH0146EJ0100 Rev.1.00 872
Sep 22, 2011
Figure 19-4. Timing of Reset in STOP Mode by RESET Input
Delay
Normal
operation
CPU status
Reset period
RESET
Internal reset signal
STOP instruction execution
Stop status
(oscillation stop)
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Hi-Z
Note
Starting X1 oscillation is specified by software.
Normal operation
(high-speed on-chip oscillator clock)
Wait for oscillation
accuracy stabilization
Reset processing: 387 to 674 μs (When LVD is used)
155 to 360 μs (When LVD off)
Port pin
(except P130)
Port pin
(P130)
Note When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummy-output
as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a
reset signal to an external device, set P130 to high-level output by software.
Remark For the reset timing of the power-on-reset circuit and voltage detector, see CHAPTER 20 POWER-ON-
RESET CIRCUIT and CHAPTER 21 VOLTAGE DETECTOR.
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