RL78/G13 CHAPTER 19 RESET FUNCTION
R01UH0146EJ0100 Rev.1.00 873
Sep 22, 2011
Table 19-1. Operation Statuses During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
fIH Operation stopped
fX Operation stopped (the X1 and X2 pins are input port mode)
Main system clock
fEX Clock input invalid (the pin is input port mode)
fXT Operation stopped (the XT1 and XT2 pins are input port mode)
Subsystem clock
fEXS Clock input invalid (the pin is input port mode)
fIL
CPU
Operation stopped
Code flash memory Operation stopped
Data flash memory Operation stopped
RAM Operation stopped
Port (latch) Set P130 to low-level output. The port pins except for P130 become high impedance.
Timer array unit
Real-time clock (RTC)
Interval timer
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Multiplier & divider, multiply-
accumulator
DMA controller
Operation stopped
Power-on-reset function Detection operation possible
Voltage detection function Operation stopped
External interrupt
Key interrupt function
High-speed CRC
CRC
operation
function
General-purpose CRC
RAM parity error detection function
RAM guard function
SFR guard function
Illegal-memory access detection
function
Operation stopped
Remark f
IH: High-speed on-chip oscillator clock
f
X: X1 oscillation clock
f
EX: External main system clock
f
XT: XT1 oscillation clock
f
EXS: External subsystem clock
f
IL: Low-speed on-chip oscillator clock
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