Renesas RL78 - Page 11

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 11 of 85
Feb. 15, 2017
(9) When reception data is abnormal
 Framing error: set P31 to Low output/High output, LED1 blinks.
 Parity error: set P33 to Low output/High output, LED2 blinks.
 Overrun error: set P31 and P33 to Low output/High output, LED1/LED2 both blink.
 Repeat step (9).
(10) UART0 reception status initialization
 Set variable g_status to “0” (OK).
 Set variable g_uart0_rx_count to “0” (receive count value = 0).
 Set variable g_uart0_rx_length to “1” (receive data number = 1).
 Set variable gp_uart0_rx_address to receive data pointer.
(11) Set variable g_uart0rxend to “0” (UART0 not received).
(12) INTP11 Operation start
 Set IF1H register PIF11 bit to “0” (interrupt request signal not generated).
 Set MK1H register PMK11 bit to “0” (interrupt processing enabled).
(13) Repeat steps (6) to (12).