Renesas RL78 - SAU0 Initialization

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 47 of 85
Feb. 15, 2017
5.9.6 SAU0 initialization
Figure5.10 shows the flowchart for SAU0 initialization.
R_SAU0_Create
SAU0 reset release
Supply clock to SAU0
Select SAU0 operation clock
CK00 = f
CLK /2
UART0 initializatoin
R_UART0_Create()
return
SPS0 register ← 0001H : f CLK /2
PRR0 register
SAU0RES bit ← 1 : SAU0 is in reset state
SAU0RES bit ← 0 : SAU0 reset is released
PER0 register
SAU0EN bit ← 1 : SAU input clock supply ena bl ed
Figure 5.10 SAU0 Initialization