Renesas RL78 - Page 48

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 48 of 85
Feb. 15, 2017
・Peripheral reset control register 0 (PRR0)
Release SAU0 from reset state.
SAU0 Reset Release
・Peripheral enable register 0 (PER0)
Enable clock supply to SAU0.
SAU0 Clock Su
pp
l
y
Symbol: PRR0
7 6 5 4 3 2 1 0
0 IICA1RES ADCRES IICA0RES 0 SAU0RES 0 TAU0RES
x x x x x
0 x x
Bit 2
SAU0RES Control of serial array unit reset release
0 Reset release of serial array unit
1 Reset state of serial array unit
Symbol: PER0
7 6 5 4 3 2 1 0
RTCEN IICA1EN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN
x x x x x
1 x x
Bit 2
SAU0EN Input clock supply control of serial array unit 0
0 Stops input clock supply
1 Enables input clock supply