Renesas RL78 - Page 60

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 60 of 85
Feb. 15, 2017
INTP
A
ll Interru
p
ts Disable
・Interrupt request flag register (MK0L/MK1H)
Disable all INTP interrupts.
・Interrupt request flag register (IF0L/IF1H)
Clear all INTP interrupt request flags.
Symbol: MK0L
7 6 5 4 3 2 1 0
PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK
1 1 1 1 1 1 x x
Bit 7 – 2 (n = 0 - 5)
PMKn Interrupt processing control
0 Enables interrupt processing
1 Disables interrupt processing
Symbol: MK1H
7 6 5 4 3 2 1 0
PMK11 PMK10 PNK9 PMK8 PMK7 KRMK TMKAMK ADMK
1 1 1 x x x x x
Bit 7 – 5(n = 9 - 11)
PMKn Interrupt processing control
0 Enables interrupt processing
1 Disables interrupt processing
Symbol: IF0L
7 6 5 4 3 2 1 0
PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF
0 0 0 0 0 0 x x
Bit 7 - 2 (n = 0 - 5)
PIFn Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state
Symbol: IF1H
7 6 5 4 3 2 1 0
PIF11 PIF10 PIF9 PIF8 PIF7 KRIF TMKAIF ADIF
0 0 0 x x x x 0
Bit 7 – 5(n = 9 - 11)
PIFn Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state