Renesas RL78 - Page 65

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 65 of 85
Feb. 15, 2017
UART0 Reception Complete/Reception Error Interrupt Enable
・Interrupt request flag register (MK0H)
Enable UART0 interrupts.
・Interrupt request flag register (IF0H)
Clear all UART0 interrupt request flags.
Symbol: IF0H
7 6 5 4 3 2 1 0
ST1IF
CSIIF10
IICF10
TMIF00 SREIF0 0 0
SRIF0
CSIIF01
IICIF01
STIF0
CSIIF00
IICIF00
PIF6
x x 0 x x 0 x x
Bit 5
SREIF0 Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state
Bit 2
SRIF0 Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state
Symbol: MK0H
7 6 5 4 3 2 1 0
ST1MK
CSIMK10
IICMK10
TMMK00 SREMK0 1 1
SRMK0
CSIMK01
IICMK01
STMK0
CSIMK00
IICMK00
PMK6
x x 0 x x 0 x x
Bit 5
SREMK0 Interrupt processing control
0 Enables interrupt processing
1 Disables interrupt processing
Bit 2
SRMK0 Interrupt processing control
0 Enables interrupt processing
1 Disables interrupt processing