Renesas RL78 - Page 72

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 72 of 85
Feb. 15, 2017
・Timer channel start register 0 (TS0）
Set to count enabled state.
TAU0 Channel 3 Count O
p
eration Enable
Symbol: TS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 TSH
03
0 TSH
01
0 0 0 0 0 TS03 TS02 TS01 TS00
x x x x x x x x x x x x 1 x x x
Bit 3
TS03 Operation enable (start) trigger for channel n
0 No trigger operation
1 TEmn bit is set to 1, goes to count operation enabled state.