Renesas RL78 - Page 76

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 76 of 85
Feb. 15, 2017
・Time output enable register 0 (TOE0)
Set timer output to disabled.
TAU0 Channel 1 Timer Output Disable
T
A
U0 Channel 1 Interru
p
t Disable
・Interrupt request flag register (MK1L)
Set to interrupt disabled.
・Interrupt request flag register (IF1L)
Clear interrupt request flag.
Symbol: MK1L
7 6 5 4 3 2 1 0
TMMK03 TMMK02 TMMK01 TMMK03H TMMK01H IICAMK0 SREMK1
SRMK1
CSIMK11
IICMK11
x x 1 x x x x x
Bit 5
TMMK01 Interrupt request flag
0 Enables interrupt processing
1 Disables interrupt processing
Symbol: IF1L
7 6 5 4 3 2 1 0
TMIF03 TMIF02 TMIF01 TMIF03H TMIF01H IICAIF0 SREIF1
SRIF1
CSIIF11
IICIF11
x x 0 x x x x x
Bit 5
TMIF01 Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state.
Symbol: TOE0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 TOE0
3
TOE0
2
TOE0
1
TOE0
0.
x x x x x x x x x x x x x x 0 x
Bit 1
TOE0
1
Timer output enable/disable of channel n
0 Timer output is disabled
1 Timer output is enabled