Renesas RL78 - Page 78

RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 78 of 85
Feb. 15, 2017
Symbol: MK1L
7 6 5 4 3 2 1 0
TMMK03 TMMK02 TMMK01 TMMK03H TMMK01H IICAMK0 SREMK1
SRMK1
CSIMK11
IICMK11
1 x x x x x x x
Bit 7
TMMK03 Interrupt processing control
0 Enables interrupt processing
1 Disables interrupt processing
Symbol: IF1L
7 6 5 4 3 2 1 0
TMIF03 TMIF02 TMIF01 TMIF03H TMIF01H IICAIF0 SREIF1
SRIF1
CSIIF11
IICIF11
0 x x x x x x x
Bit 7
TMIF03 Interrupt request flag
0 Interrupt request signal not generated
1 Interrupt request signal generated, goes to interrupt request state.
TAU0 Channel 3 Interrupt Disable
・Interrupt request flag register (MK1L)
Set to interrupt disabled.
・Interrupt request flag register (IF1L)
Clear interrupt request flag.