RL78/G11 UART Reception in STOP Mode Using Middle-speed On-chip Oscillator IAR
R01AN3634EJ0100 Rev.1.00 Page 9 of 85
Feb. 15, 2017
(5) main processing initialization
<Setting conditions>
UART0 reception status initialization
Set variable g_status to “0” (OK).
Set variable g_uart0_rx_count to “0” (receive count value = 0).
Set variable g_uart0_rx_length to “1” (receive data number = 1).
Set variable gp_uart0_rx_address to receive data pointer.
Baud rate setting
Set CKC register MCM1 bit to “0” (high-speed on-chip oscillator clock)
Wait until high-speed on-chip oscillator clock setting changes.
TAU0 channel 3 starts operating.
Set IF1L register TMIF03 bit to “0” (interrupt request signal not generated).
Set MK1L register TMMK03 bit t to “0” (interrupt processing enabled).
Set TS0 register TS03 bit to “1” (count operation enabled state).
Set TIS0 register bits TIS02 to TIS00 to “011B” (middle-speed on-chip oscillator clock (f
IM
).
Set TMR01 register to “1000H.
Set bits CKS011 to CKS010 to “00B” (operating clock CKm0 set in timer clock selection register
m(TPSm).
Set CS01 bit to “0” (valid edge of input signal from TImn pin).
SPLIT01 to “0” (operates as 16-bit timer).
Set bits STS012 to STS010 to “000B” (only software trigger start is valid; other trigger sources are
unselected).
Set bits CIS011 to CIS010 to “00B” (falling edge).
Set bits MD013 to MD011 to “000B” (interval timer mode).
Set MD013 bit to “0” (timer interrupt is not generated when count starts (no change to timer output).
Set TDR01 register to “1295H”.
TAU0 channel 1 starts operating.
Set IF1L register TMIF01 bit to “0” (interrupt request signal not generated).
Set MK1L register TMMK01 bit to “0” (interrupt processing enabled)
Set TOE0 register TOE01 bit to “1” (timer output enabled).
Set TS0 register TS01 bit to “1” (count operation enabled state)
Shift to HALT mode, wait until TAU0 channel 3 interrupt is generated twice.
Set CSC register HIOSTOP bit to “1” (high-speed on-chip oscillator stopped).
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