RZ Family / RZ/G, RZ/A Series 2. Functional Specifications
R01UH0990EJ0101 Rev.1.01 Page 43 of 83
Jul 28, 2022
2.3 Memory
QSPI flash memory and DDR4 SDRAM are mounted on the RTK9743U11C01000BE as external memories.
Please refer to the following for details.
2.3.1 QSPI Flash Memory
Figure 2.1 shows a block diagram of the Serial Flash Memory Interface.
The QSPI flash memory is controlled by the SPI Multi I/O Bus Controller (SPIBSC) that is with built-in to the
RZ/G2UL. This memory supports both single data rate (SDR) and double data rate (DDR) transfers at 66 MHz and 50
MHz clock frequency.
NOTE
The pull-up resistor on the clock line “RZ_QSPI0_SPCLK” is optional.
Figure 2.1 Block Diagram of Serial Flash Memory I/F
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