Instrument Design and Function Description R&S SMU200A
1007.9845.82 3.2 E-6
Fractional-N Loop
The Fractional-N Loop submodule handles fine resolution for the entire synthesizer. It contains a PLL in
which a tuneable oscillator in the range from 652.689 MHz to 676 MHz is synchronized to a reference
frequency (43.51 MHz to 45.06 MHz) obtained via fractional-N division. The divider in the reverse path
of the PLL functions only as an integer divider.
Fractional division is performed by using the SYNCON4 and RFDIV chips. The advantage of fractional
division in the reference path of the PLL is that the higher input frequency of 1040 MHz also allows
higher division factors to be implemented, which poses fewer problems with regard to resulting
spurious.
To ensure quick settling, a high reference frequency was chosen. Dynamic switchover of the control
bandwidth during settling also occurs. However, it is also possible to keep the control bandwidth
statically wide. The VCO is preset via a D/A converter.
A programmable divider at the output of the Fractional-N Loop submodule divides the oscillator output
spectrum down to a frequency range of 56.7 MHz to 117.55 MHz. This step improves phase noise and
spurious suppression by the corresponding divider factor.
The output frequency is used by the Main Loop submodule as a reference frequency.
Step Frequency Unit
The Step Frequency Unit handles coarse resolution for frequency synthesis. Within a given frequency
grid, it creates discrete frequencies in the range from 693.33 MHz to 1500 MHz that are derived from
the 1040 MHz reference frequency.
This is done by using a programmable divider (RFDIV) to divide the 1040 MHz fixed frequency into
three frequencies of 104 MHz to 115.55 MHz (division factors of 9, 9.5 and 10). These frequencies are
multiplied by factors of 6 to 14 using a frequency multiplier, and the required frequency characteristic is
then selected by means of a tuneable bandpass filter.
The level of the output signal of the Step Frequency Unit is calibrated by means of a level preset and is
used by the Main Loop submodule as an RF signal for down-conversion in a PLL.
Main Loop
The Main Loop submodule generates the frequency spectrum from 731 MHz to 1512.5 MHz. It consists
of four tuneable oscillators that each cover a segment of the entire spectrum. The reverse path of the
PLL contains a mixer that down-converts the VCO signal and the output signal of the Step Frequency
Unit to the reference frequency of 56.7 MHz to 117.55 MHz. An analog frequency phase detector
(mixer) compares the down-converted frequency with the output signal of the Fractional-N Loop
submodule. To ensure proper settling, a digital PD (RFDIV) is parallel-connected during frequency
switchover.
The frequency algorithm prevents mixture products from crossing the reference frequency (it would not
be possible to suppress them as spurious near the carrier).
The control bandwidth of the Main Loop submodule is approx. 200 kHz. To ensure that the control loop
always locks on the correct mixer sideband, pretuning of the VCOs is provided.
The output signal of the Main Loop submodule is directly forwarded to the Frequency Doubler module.
The input signal of the Frequency Doubler module covers the frequency range from 750 MHz to 1512.5
MHz.
To Next Page
Loading...
