Sagetech MXS - Page 49

MXS System Description and Installation Manual UM06945
© Sagetech Avionics 2022 Proprietary Confidential Page 49 of 56
Byte
Name
Bit
Built-In Test (BIT)
What triggers it?
What happens?
What to do about?
BIT0
7
(msb)
Power-On Tests
Pass
Checks RAM, ROM, I/O, Timing, CPU
instruction integrity, and calibration data.
If any of the Power Up BIT tests are failing MXS sets
this BIT. Power-Up Fail Flag is latched causing a XPDR
fail flag in the ACK message. Persists until next power
cycle.
Request Status message to
get details about the specific
BIT failure.
6
Continuous Tests
Pass
Checks 1030MHz/1090MHz receivers,
services the watchdog timer, checks for an
erroneous ICAO address, monitors the 53V
supply, detects memory parity errors and
SEUs of FPGA programming, monitors
input supply voltage, and monitors internal
temperature.
If any of the continuous BIT tests are failing MXS sets
this bit. Continuous Bit Fail Flag is latched causing
XPDR or System Fail flag in the ACK message.
Condition in which a test begins to pass is defined for
each test in the table entries below. If Watchdog
timer, memory parity or SEU tests fail the MXS will
reset the processor
Request the status message
to get details about the
specific BIT failure. The bit is
cleared if failing tests begin
to pass.
5
Reserved
4
Processor Test
Passed
The MXS performs a test of the processor
instruction set and passes the numerical
result of the test to the FPGA for
verification. The MXS accepts the result of
this test (Pass or Fail) from the FPGA.
Power-Up Fail Flag is latched causing a XPDR fail flag in
the ACK message. Persists until next power cycle.
If flagged, first remedy is to
power cycle the unit. If error
is still triggered, then the
unit is damaged.
3
Flash Image CRC
Valid
The MXS computes and verifies the CRC of
the software Executable Object Code
(EOC), the Firmware Programming file
(FPF), and the configuration parameters
stored in non-volatile memory.
Power-Up Fail Flag is latched causing a XPDR fail flag in
the ACK message. Persists until next power cycle.
If flagged, first remedy is to
power cycle the unit. If error
is still triggered, then the
unit is damaged.
2
Memory Test
Passed
The MXS performs a test of the processor
RAM by executing a “walking ones” test to
verify memory addressing and that each
bit can successfully contain a 0 and a 1.
Power-Up Fail Flag is latched causing a XPDR fail flag in
the ACK message. Persists until next power cycle.
If flagged, first remedy is to
power cycle the unit. If error
is still triggered, then the
unit is damaged.
1
Calibrated
The calibration data checksum test passed,
otherwise the bit is cleared
Power-Up Fail Flag is latched causing a XPDR fail flag in
the ACK message. Persists until next power cycle.
Unit will function but not at performance specification
Return unit for calibration.
Use of uncalibrated units
could cause permanent
damage.
0
Reserved
Reserved
Reserved
Reserved