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LC-32LE530
LC-40LE530
to the DDR2-667 (5-5-5) specification. All of the control and address inputs are
synchronized with a pair of externally supplied differential clocks. Inputs are latched at the
cross point of differential clocks (CLK rising and CLK falling). All I/Os are synchronized
with a single ended DQS or differential DQS- DQS pair in a source synchronous fashion.
10.2. Features
x Power Supply: VDD, VDDQ = 1.8 V± 0.1 V
x Double Data Rate architecture: two data transfers per clock cycle
x CAS Latency: 3, 4, 5, 6 and 7
x Burst Length: 4 and 8
x Bi-directional, differential data strobes (DQS andDQS ) are transmitted / received
with data
x Edge-aligned with Read data and center-aligned with Write data
x DLL aligns DQ and DQS transitions with clock
x Differential clock inputs (CLK and CLK )
x Data masks (DM) for write data
x Commands entered on each positive CLK edge, data and data mask are
referenced to both edges of DQS
x Posted CAS programmable additive latency supported to make command and data
bus efficiency
x Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
x Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for
better signal quality
x Auto-precharge operation for read and write bursts
x Auto Refresh and Self Refresh modes
x Precharged Power Down and Active Power Down
x Write Data Mask
x Write Latency = Read Latency - 1 (WL = RL - 1)
x Interface: SSTL_18
10.3. Electrical Characteristics
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