53
LC-40SH340E
LC-40SH340K
16. USB2.0 to Fast Ethernet – ASIX AX88X72A (U171)
16.1. General Description
The AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet controller is a high
performance and highly integrated ASIC which enables low cost, small form factor, and simple plug-and-
play Fast Ethernet network connection capability for desktops, notebook PC’s, Ultra-Mobile PC’s, docking
stations, game consoles, digital-home appliances, and any embedded system using a standard USB port.
The AX88772A/AX88172A features a USB interface to communicate with a USB Host Controller and is
compliant with USB specification V1.1 and V2.0. The AX88772A/AX88172A implements 10/100Mbps
Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards with 24KB of embedded SRAM for
packet buffering. The AX88772A/AX88172A integrates an on-chip 10/100Mbps Ethernet PHY to simplify
system design.
The AX88172A provides an optional External Media Interface (EMI) for external PHY or external MAC for
different application purposes. The EMI can be a media-independent interface (MII) for implementing
100BASE-FX Ethernet or HomePNA functions. The EMI can also be a Reverse-MII or Reverse Reduced-MII
(Reverse-RMII) for glueless MAC-to-MAC connections to any MCU with Ethernet MAC MII or RMII interface.
In addition, the EMI can be configured to Dual-PHY mode allowing AX88172A to act as an Ethernet PHY or
USB 2.0 PHY for external MAC device that needs Ethernet and USB interfaces in their system applications.
The optional serial interface such as I2C, SPI, and UART are provided as a control channel from the USB
Host Controller to communicate with the external MCU chip.
16.2. Features
Single chip USB 2.0 to 10/100M Fast Ethernet controller – AX88772A
USB Device Interface
x Integrates on-chip USB 2.0 transceiver and SIE compliant to USB Spec 1.1 and 2.0
x Supports USB Full and High Speed modes with Bus-Power or Self-Power capability
x Supports 4 or 6 programmable endpoints on USB interface
x High performance packet transfer rate over USB bus using proprietary burst transfer
mechanism
x Supports USB to Ethernet bridging or vice versa in hardware
Fast Ethernet Controller
x Integrates 10/100Mbps Fast Ethernet MAC/PHY
x IEEE 802.3 10BASE-T/100BASE-TX compatible
x Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX)
x Embedded 16KB SRAM for RX packet buffering and 8KB SRAM for TX packet buffering
x Supports both Full-duplex with flow control and
x Half-duplex with backpressure operation
x Supports 2 VLAN ID filtering, received VLAN Tag (4 bytes) can be stripped off or preserved
MAC/PHY loop-back diagnostic capability
Support Wake-on-LAN Function
15.
15.2
15.1
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General
Weight and Dimensions
