•
Read
For plane read data
from
the VRAM, data
to
be
read
by the
CPU
are arranged in accordance
with
the
direction
of
the read
format
register
(RF).
VAO
-7
!Planes. I.
Ill
vco,.. 7
!P1ane1,lll.l\")
RFregis\er
WFrSfjiSIBf
* Logic circuit
Read
data
from
the VRAM and
write
data
from
the
CPU
are subjected
to
logical operation
(OR,
XOR,
RESET,
etc.) and its result is used
for
the
write
data.
VRAM access
timing
1)
MZ-700 mode
See
separate page
for
display
timing
chart.
The VRAM is configured in the
following
manner in
this instance.
VA
VC
(option)
$0000
Not used
$2000
Not
used
CG
area
$3000
TEXT area
ATB area
$3FFF
13
As the
PCG
method is adopted
for
the MZ-700 mode,
the text and ATB areas are actually mapped
to
$0000
-
$DFFF.
So, the VRAM address has the following
relation
with
the display character position.
2
DOOO
0001
2 0028
2)
MZ-800 mode
3
0002
40
~====~
-----~
I
I
I I
------~~~
As the bit map method is used
for
the MZ-800 mode,
it
is possible
to
four
screens
of
320 x
200
dots and
two
screens (maximum)
of
640
·x
200
dots.
The cycle steal method is used
for
this mode.
i) 320 x
200
dots
See
separate page
for
the
timing
chart dL.ring
display and
CPU
read timing.
What
is pseudo cycle steal
With the MZ-800, the pseudo cycle steal method is
adopted
for
VRAM accessing.
LOAD~
u
x~~~s
==:::x
DISP.
address X
CPU
address X
DISP.
address
~
I
·I
DISP.
cicle
CPU
cicle
DISP.
cicle
As shown in the figure, a next display data fetch and
CPU
accessing are multiplexed during a display period.
Because accessing
of
the VRAM while characters are on
display causes the screen
to
blink
with
the MZ-700
mode,
it
awaits
for
blinking
to
complete before acces-
sing
of
the VRAM. But,
with
the cycle steal method it
enhances faster screen processing
as
it
enables to
access the VRAM during a display period. Because
it
is
not a complete cycle steal
with
the MZ-800 but
timing
is
taken using a
wait
in order
to
synchronize
with
the
CPU
cycle
for
accessing
from
the
CPU,
it
is therefore called
"pseudo cycle steal".
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