VRAM
to
CPU
interface
• As the
CRTC
bus is completely separated
from
the
CPU
bus, read and write
of
the VRAM is carried out
through the
CRTC.
Therefore, interfacing
with
the
CPU
is done via the read register
or
write
register in
the
CRTC.
• VRAM access by the
CRTC
is done under the pseudo
cycle steal mode.
• Not
only
read and write are
for
the accessing
with
the
CPU,
it
permits to read
multiple
number
of
screen
data
logical operational results and
to
write
the
read-modify-write
of
the logical operational results
for
the data already written. So, it has
two
registers
of
the read
format
register and the write
format
register.
•
lt
permits
CPU
access
to
the non-display plane in the
display mode according to the
8/
A bit and it enables
selection
of
data buffer and
two
screens, when the
32
KB
VRAM
is
used.
a)
Read
format
register
(RF)
(OUT &
CD)
MSB
LSB
IV
Ill
II
• NOTE: Same
as
the bit B/A
of
the
write
format
register.
• SRCH/SI
NG
"0":
Single calor data read .....
Reads the data
of
the calor plane, I, II, Ill,
or
IV,
specified by
"1
".
NOTE:
Only one item should
be
"1"
out
of
I,
II,
Ill, and IV.
If
it is
"1"
for
more than
two
or
non-existence
of
the VRAM may not
assure the data read.
"1
":
Specified col or search .....
"1"
is returned
for
the
bit
of
the col
or
specified by
0/1
of
I, II,
m,
and IV.
NOTE:
Depending on the display more, calor
combination is permitted
for
the bit com-
bination
of
I, II, Ill,
IV;
Ill,
IV;
I,
II;
I; and
Ill. Bit combination otherwise will
be
dis-
regarded.
(ex. For the
640 x 200, 4-color mode,
combination becomes
possible for I and
Ill, and
II
and
IV
are disregarded.
•
B/A
CPU
access plane change
MZ-800
~
"0":
Frame A access .....
Accesses the
frame
A (planes I and
II
for
the 320
x 200, 4-color mode; plane I
for
the 640 x
200,
1-color mode).
"1":
FrameBaccess
.....
Accesses the
(planes m and
IV
for
the
320
X
200,
4-color mode; plane
II
for
the 640 x
200,
1-color
mode).
• I, II, Ill,
IV
..... Calor plane designation.
18
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