800
MODE
(640 x 200
dot)
DISP.
cycle
CPU
cycle
OISP.
cycle
VRAS
VCAS
VOE
vAoo-7
===x_~R=ow==~x;==c=o
7
L~X~
____
co_L_.
--~X~~==~x~==~======~----~X~~==~x~====~-
N+1th
adr.
Nth adr.
CPU
adr. latch DATA
N+2th
adr.
VAO-
7
I
plane
Nth
DATA
I
plane
N+l
th DATA
CPU
read
OA
TA
VC
0-7
Ill
plane Nth OAT A
Ill
plane
N+lth
DATA
CPU
read
OA
TA
LOAD
(sift register)
LJ
CPU
and VRAM accessing
1.
Accessing
of
the VRAM by
the
CPU
is carried
out
in
the cycle
steal mode (MZ-800
mode
only)
during
the
flyback period
of
the display urider the control
of
the
CRT
controller.
2.
Even when there is no accessing
from
the
CPU
in
the
CPU
cycle, such
as
VRAS, VCAS,
VOE,
etc. are
outputted in the timing
of
the read cycle at all times.
3.
Write
to
the VRAM is carried out after logical
op~ra
tion
of
the read and
write
data by means
of
the
read-modify-write method.
But, in the case
of
the
320
x 200, 16-color mode, data are
written
in
two
CPU
cycles
as
there is a need
of
writing
to
Plane
N.
See separate paper
for
timing
chart.
4.
CPU
wait
1)
Write
• As there is a one-byte buffer in the
CRT
controller,
write
to the VRAM
from
the
CPU
is carried
out
through the buffer. But, actual
write
to
the VRAM is
CPU
cycle(D
VRAS
VCAS
VOE
LJ
\._j
done by the
CRT
controller. Therefore, there
would
be no need
of
wait
under
almost any condition in the
MZ-800 mode.
• Even in the MZ-700 mode, wait
is·
issued when there
are
more
than
two
writes in a display period.
Flyback period
Display period
_Jt:=·
=======r---
HBLN
CPU.WR
U \
VRAM.WR--------~<D~•-------+--~--~-®~-t.
WAIT
2)
Read
Wait is issued along with the
CPU
write action both
during
displaying
and
flyback periods to perform
reading operation in synchronization with the
CPU
cycle.
OISP.
cycle
CPU
cycle®
VAO
0-7
~
ROW
X
COL.
X X X X ROW
X.____:C:.:O:.=L'--
_____
x.
~~====~==-;------'
CPU
adr. latch DATA
I,
Ill
plane
DISP.
adr.
11,
IV
plane
VRWR
DISP.
DATA
16
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