Siemens ET 200S - Page 148

Commissioning and Diagnostics
6-24
Distributed I/O System ET 200S
EWA 4NEB 780 6024-02 07
Evaluating Hardware Interrupts with STEP 7
In the event of a hardware interrupt, the CPU interrupts the processing of the user
program and processes the process interrupt block OB 40 instead.
The module channel that triggered the hardware interrupt is entered in the start
information of OB 40 in the OB40_POINT_ADDR variable. In the figures below you
will find the assignment to the bits of the local double word 8.
Hardware Interrupts in the Case of:
2DI 24 VDC High Feature and 4DI 24 VDC High Feature Electronic Modules:
1
Bit no.
3130
29 28 2726
LD 81
LB 8
LB 9
25 24
Rising edge: Channel 2
Rising edge: Channel 0
Rising edge: Channel 3
LB 11
0
1
Rising edge: Channel 1
11
LB 10
2DI
4DI
Figure 6-18 Start Information of OB 40: Which Event Triggered a Hardware Interrupt with Digital Input
Modules
Hardware Interrupts with:
2AI U High Speed, 2AI I 2WIRE High Speed, and 2AI I 4WIRE High Speed
Electronic Modules:
1
Bit no.
3130 29 28 2726
LD 8
1
LB 8
25 24
Lower limit value violated: Channel 0
Upper limit value violated: Channel 1
LB 11
0
1
LB 10
1
2322 21 20 1918
1
LB 9
17 16
Lower limit value violated: Channel 0
Upper limit value violated: Channel 1
Figure 6-19 Start Information of OB 40: Which Event Triggered a Hardware Interrupt with Analog Input
Modules
You will find a description of the OBs 40 in the Reference Manual System and
Standard Functions.