Counting
4.1 Configuration method 2xCount
Digital input/Digital output module DIQ 16x24VDC/0.5A 8xM12 (6ES7143-5AH00-0BA0)
46 Manual, 03/2019, A5E38688112-AC
4.1.2.6 Explanations for the feedback interface
Table 4- 11 Explanations for the feedback bits
This value supplies the current count value for the respective counter.
This bit returns the current signal state of the count output.
STS_GATE Together with the hardware gate the software gate forms the internal gate. This bit shows
the state of the internal gate for the respective counter. The module only counts when the
internal gate is open.
0 means: Internal gate closed / counter does not count
1 means: internal Tor open / counter counts
After a POWER OFF / ON or a change in the parameterization, all the values of the
changed counter are transferred again to the module. In the process the internal gate of
the respective counter is closed and the count value is set to the start value. Close and
open the respective SW gate to restart the counting process.
When the PROFIBUS interface model is used, the CPU/Master automatically generates
the "rising edge" signal after disconnection/reconnection of the communications. This con-
tinues the counting process.
STS_SW_GATE This bit shows the status of the software gate.
0 means: Software gate closed
1 means: Software gate open
LD_STS_SLOT This bit indicates through a status change (toggling) for the respective counter that loading
of the control interface has been carried out successfully.
LD_ERROR This bit indicates for the respective counter that an error has occurred during loading of the
control interface.
The load value was not accepted.
One of the following conditions is fulfilled:
• Low counting limit > Count value
• Low counting limit > Start value
• Low counting limit > Comparison value
• Count value > High counting limit
• Start value > High counting limit
• Comparison value > High counting limit
• Low counting limit ≥ High counting limit
• No valid load request in LD_SLOT
EVENT_UFLW This bit shows for the respective counter whether an underflow (value dropped below the
low count limit) has occurred.
You reset the state by acknowledging with RES_EVENT_UFLW.
EVENT_OFLW This bit shows for the respective counter whether an overflow (value exceeded the high
count limit) has occurred.
You reset the state by acknowledging with RES_EVENT_OFLW.
EVENT_CMP This bit shows for the respective counter whether a comparison event with the comparison
value has occurred.
You reset the state by acknowledging with RES_EVENT_CMP.
The EVENT_CMP bit is not set if the count value is set to the start value.
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