Counting
4.2 Configuration method 4xCount
Digital input/Digital output module DIQ 16x24VDC/0.5A 8xM12 (6ES7143-5AH00-0BA0)
Manual, 03/2019, A5E38688112-AC
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RES_EVENT_UFLW_ACK This bit shows for the respective counter whether the resetting of the event bit
RES_EVENT_OFLW_ACK This bit shows for the respective counter whether the resetting of the event bit
EVENT_OFLW is active.
RES_EVENT_CMP_ACK This bit shows for the respective counter whether the resetting of the event bit
Complete acknowledgment principle
Storing bits are acknowledged in accordance with the complete acknowledgment principle.
The figure below shows an example for the course of the complete acknowledgment
principle at an overflow:
The feedback bit EVENT_OFLW is set as a storing event at an overflow bit.
The set the control bit RES_EVENT_OFLW in order to initiate resetting of EVENT_OFLW.
The feedback bit RES_EVENT_OFLW_ACK is set when the resetting of EVENT_OFLW has
You reset the control bit RES_EVENT_OFLW .
The feedback bit RES_EVENT_OFLW_ACK is reset.
Figure 4-10 Acknowledgment principle
Note
When you have initiated the resetting of an event bit, you have to wait for the respective
feedback bit. You can initiate a further reset subsequently.
SW gate or HW gate (0-1 transition) resets all event bits.