Data record TMFASTControlREC
C.1 Use and structure of TMFASTControlREC (data record 100)
Technology module TM FAST (6ES7554-1AA00-0AB0)
64 Equipment Manual, 04/2023, A5E52301130-AA
Structure of data record 100 (TMFASTControlREC) for reading
The following table shows the structure of data record 100 for reading.
Table C- 2 Read data record 100
1
status:
terface
B
command
possible
B
interface
disabled
000B: No TM FAST application available
B
: TM FAST application is loaded but
not active
B
command
possible
B
interface
enabled
B
: TM FAST application is loaded and
active
Last error code (see following table) (BYTE)
System logic version in the FPGA: Major (BYTE)
System logic version in the FPGA: Minor (BYTE)
System logic version in the FPGA: Patch (BYTE)
System logic version in the FPGA: Letter (CHAR)
User logic version in the FPGA: Major (BYTE)
User logic version in the FPGA: Minor (BYTE)
User logic version in the FPGA: Patch (BYTE)
User logic version in the FPGA: Letter (CHAR)
Application ID in the FPGA (CHAR[8])
Number of bytes of TMFASTUserWriteREC (BYTE)
Number of bytes of TMFASTUserReadREC (BYTE)
1
Bus terminating resistor
for CH0:
0000B: RS485 channel, bidirectional
0001B: RS422 input channel
B
rameter assignment in
data record 128 (Page 58)
0010B: RS422 output channel
0100B: TTL output channel
B
Parameter CH1:
see Byte 24
Parameter CH2:
see Byte 24
Parameter CH3:
see Byte 24
Parameter CH4:
see Byte 24